Ordered Chaos: Imposing Logical Structure in Nanotechnology Substrates

We expect emerging nanotechnology substrates to consist of a vast number of small processing nodes that are randomly assembled, have defect rates as high as 30%, and have globally asynchronous communication. Directly constructing an architecture on such a substrate presents many challenges to a system designer. An alternative approach, that would ease the constraints faced by a nanotechnology architect, would be to provide a layer of abstraction between the physical substrate and the architectural design space that logically structures the system components. We propose an abstraction layer that can impose a defect-free logical grid on randomly oriented and randomly connected nodes. This layer is based on the observation that logical neighbors in a network need not be constrained to physical neighbors but instead can be connected through a series of communication hops. Our distributed ordering algorithm guarantees that all nodes reachable from a micro-world connection node will be included in the logical grid.